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toshiba TB62726AFNA 16-bit constant current led driver with operating supply of 3.3v to 5v t b 6 2 7 2 6 a f n a data sheet version no. date note inspect 001 2002-4-26 target spec by afna 002 2002-5-15 the setup of the tentative spec of iout 003 2002-5-21 evaluation set of iout spec. 004 2002-5-28 the reflection of the test spec. 005 2002-6-1 some of proofreading 006 2002-6-22 some of proofreading 007 2002-10-1 a format is changed. 008 2002-10-11 iout spec. reexamination 009 2002-11-6 final spec. we agree this specification. company date signature TB62726AFNA(ver.9) 2002,nov.6 th page00/11
toshiba TB62726AFNA toshiba bi-cmos integrated circuit silicon monolithic t b 6 2 7 2 6 a f n a 16-bit constant current led driver with operation supply of 3.3v to 5v the TB62726AFNA is comprised of constant-current drivers designed for leds and led displays. the output current value can be set using an external resistor. as a result, all outputs will have virtually the same current levels. this driver incorporates a 16-bit constant-current output, a 16-bit shift register, a 16-bit latch and a gate circuit. these drivers have been designed using the bi-cmos process. feature *output current capability and the number of output: 90 ma x 16 outputs *constant current range : 2 to 90 ma *application output voltage : 0.7v (output current 2 to 80ma) 0.4v (output current 2 to 40ma) *for anode common led *input signal voltage level : 3.3v-5.0v cmos level (schmitt trigger input) *power supply voltage range vdd=3.0 to 5.5v *muximum output terminal voltage 17v *serial and parallel data transfer rate 20 mhz (min., cascade connection) *operation temperature range topr = -40 to 85 degrees *package : p-ssop24-150-0.635 *current accuracy (not used dot-current correction.) output current accuracy output voltage between bits between ics current >= 0.4v +/- 4 % >= 0.7v +/- 12 % 2 to 40 ma 2 to 90 ma TB62726AFNA (ver.9) 2002, nov. 5 th page 1/11 TB62726AFNA p-ssop24-150-0.635
toshiba TB62726AFNA package and pin layout ( top view ) warnings : short-circuiting an output terminal to gnd or to the power supply terminal may broken the device. please take care when wiring the output terminals, the power supply terminal and the gnd terminals. block diagram truth table clock latch enable serial-in out0 --- out7 --- out15 serial-out positive edge h l dn dn --- dn-7 --- dn-15 dn-15 positive edge l l dn+1 no change dn-14 positive edge h l dn+2 dn+2 --- dn-5 --- dn-13 dn-13 negative edge x l dn+3 dn+2 --- dn-5 --- dn-13 dn-13 negative edge x h dn+3 off dn-13 note 1: out0~out15=on when dn=h ; out0~out15=off when dn=l in order to ensure that the level of the power supply voltage is correct, an external resistor have to c onnected between r-ext and gnd. TB62726AFNA (ver.09) 2002, nov. 6 th page 2/11 out14 out15 enable serial-out r-ext vdd gnd serial-in clock latch out0 out1 out13 out12 out11 out10 out9 out8 out7 out6 out5 out4 out3 out2 r-ext enable latch serial-in clock out0 out1 out15 serial-out i-reg q st d q st d q st d d q ck d q ck d q ck
toshiba TB62726AFNA timing diagram warning : latch circuit is leveled-latch circuit. be careful because it is not triggered-latch circuit. note 2 : the latches circuit holds data by pulling the latch terminal low. and, when latch terminal is a high-level, latch circuit doesn?t hold data, and it passes from theinput to the output. when enable terminal is low-level, output terminal out0~out15 respond to the data, and on & off does. and, when enable terminal is a high-level, it offs with the output terminal regardless of the data. TB62726AFNA (ver.09) 2002, nov. 6 th page 3/11 clock serial-in latch enable out0 out1 out3 out15 serial-out 5v 0v 5v 0v 5v 0v 5v 0v on off on off on off on off 5v 0v n=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
toshiba TB62726AFNA terminal description pin no. pin name function 7 gnd gnd terminal for control logic 8 serial-in input terminal for serial data for data shift register 9 clock input terminal for clock for data shift on rising edge 10 latch input terminal for data strobe when the latch=high-level, data is no latched. when ithe latch=low-level, data is latched. 1 to 2, 11 to 24 out 0 to 7 constant-current output terminals 3 enable input terminal for output enable. all outputs (out0 ~ out15 ) are turned off, when the enable=high-level. and are turned on, when the enable=low-level. 4 serial-out output terminal for serial data input on serial-in terminal 5 r-ext input terminal used to connect an external resistor. this regulated the output current. 6 vdd 3.3v - 5v supply voltage terminal. equivalent circuit of inputs and output TB62726AFNA (ver.09) 2002, nov. 6 th page 4/11 enable vdd gnd vdd gnd latch vdd gnd clock, serial - in vdd gnd internal data serial - out 1. enable terminal 2. latch terminal 3. clock,serial-in terminal 4. serial-out terminal r(up) r(down) gnd out 0 to 15 5. out0 to 15 terminal parasitic diode 200k 250k
toshiba TB62726AFNA absolute maximum ratings characteristics symbol rating unit supply voltage v dd +6 input voltage v in -0.2 to vdd+0.2 v output current i out +90 ma/ch output voltage v out -0.2 to 17 v power dissipation p d 1 0.89 w thermal resistance r th(j-a) 140 (free air) degree/w operating temperature t opr -40 to 85 storage temperature t stg -55 to 150 degree note 3 : subtract 7.10mw/degree every time an ambient temperature exceeds 25 times once. recommended operating condition ( vdd=4.5~5.5v, topr = -40~85 degree, unless otherwise noted. ) characteristics symbol condition min typ max unit supply voltage v dd - 3 - 5.5 v output voltage v out (on) - - 0.7 4 v output current i out each dc 1 circuit 2 - 80 ma/ch i oh i ol serial-out - - -1 - - 1 ma input voltage v ih v il - 0.7xvdd - vdd+0.15 -0.15 - 0.3xvdd v clock frequency f clk latch pulse width t w latch clock pulse width t w clock cascade connected - - 20 mhz 50 - - 25 - - enable pulse width when the pulse of the low level is inputted to the enable terminal held in the h level. t w enable upper i out =20ma 2000 - - lower i out =20 ma 3000 - - ns setup time for clock terminal t setup 1 hold time for clock terminal t hold setup time for /latch terminal t setup 2 - 10 - - 10 - - 50 - - TB62726AFNA (ver.09) 2002, nov. 6 th page 5/11
toshiba TB62726AFNA electrical characteristics ( vdd=3v to 5.5v, topr=25degree unless otherwise noted.) characteristics symbol condition min typ max unit supply voltage v dd normal operation 3.0 - 5.5 v output current i out 1 v out =0.4v,v dd =3.3v i out 2 v out =0.4v,v dd =5v r ext = 490 ohm 31.96 36.20 40.54 31.59 35.90 40.20 i out 3 v out =0.7v,v dd =3.3v i out 4 v out =0.7v,v dd =5v r ext = 250 ohm 63.63 72.30 80.97 62.75 71.30 79.95 ma output current error between bits d iout 1 v out =0.4v, r ext =490 ohm d iout 2 v out =0.4v, r ext =250 ohm all output on - +/-1 +/-4 % output leakage current input voltage i oz v out =15v - - 1 ua input voltage v in - 0.7vdd - vdd - gnd - 0.3vdd v sout terminal voltage v ol i ol =+1 ma, vdd=3.3v - - 0.3 i ol =+1 ma, vdd=5v - - 0.3 v oh i oh =-1 ma, vdd=3.3v . 3 - - i oh =+1 ma,vdd=5v 4.7 - - v output current supply voltage regulation %/v dd when v dd is changed 3v to 5.5v - -1 -5 %/v pull up resistor r (up) enable terminal pull down resistor r (down) latch terminal . 115 230 460 supply current i dd(off) 1 r ext =open, v out =15v - 0.1 0.5 i dd(off) 2 r ext =490ohm i dd(off) 3 r ext =250ohm all output off, v out =15v . 1 3.5 5 . 4 6 9 i dd(on) 1 r ext =490ohm all output on, v out =0.7v - 9 15 ta= -40degree, same as the avobe. - - 20 i dd(on) 2 r ext =250ohm all output on, v out =0.7v - 18 25 t a = -40 degree, same as the avobe. - - 40 ohm TB62726AFNA (ver.09) 2002, nov. 6 th page 6/11
toshiba TB62726AFNA switching characterictics (topr=25degree, unless otherwise noted ) characteristics symbol condition min typ max unit propagation delay t plh 1 clk-outn, latch=?h?, enable=?l? - 150 300 t plh 2 latch-outn, enable=?l? - 140 300 t plh 3 enable-outn, latch=?h? - 140 300 t plh clk-serialout 3 6 - t phl 1 clk-outn, latch=?h?, enable=?l? - 170 340 t phl 2 latch-outn, enable=?l? - 170 340 t phl 3 enable-outn, latch=?h? - 170 340 t plh clk-serial-out 4 7 - output rise time t or voltage waveform 10%~90% 40 85 150 output fall time t of voltage waveform 90%~10% 40 70 150 ns maximum clk rise time t r maximum clk fall time t f when not on pcb - - 5 - - 5 us condition : (refer to test circuit) topr=25 degree, v dd =v ih =3.3v and 5v, v out =0.7v, v il =0v,r ext =490ohms, v l =3.0v, r l =60ohms,c l =10.5pf note 4 : if the device is connected in a cascade and tr/tf for the waveform is large, it may not be possible to achieve the timing required for data transfer. please consider the timings carefully. test circuit TB62726AFNA (ver.09) 2002, nov. 6 th page 7/11 i dd i ol v ih ,v il r-ext serial-in latch clock out0 out15 serial-out enable vdd r l c l c l v l gnd i ref function generator v dd =v ih =3.3v v il =0v t r = t f = 10ns (10% to 90%) logic input waveform
toshiba TB62726AFNA timing waveform TB62726AFNA (ver.09) 2002, nov. 6 th page 8/11 t wclk t plh / t phl 50% 50% 50% 50% 50% 1. clock ,serial-in, serial-out clock serial-in serial-out 2. clock, serial-in , latch, enable, outn t hold 50% clock serial-in latch 50% 50% t w lat t setup 1 t setup 2 enable 50% 50% t w ena t setup 3 50% outn 3. outn t of t or 90% 90% 10% 10% outn t plh 1 / t phl 1 t plh 2 / t phl 2 t plh 3 / t phl 3
toshiba TB62726AFNA output current vs duty (leds turn on rate) TB62726AFNA (ver.09) 2002, nov. 6 th page 9/11 0 20 40 60 80 100 duty - turn on rate (%) 0 20 40 60 80 100 iout(ma) TB62726AFNA duty(%)-iout(ma) on pcb topr= 25 degree vdd=5.0v, vce=1.0(v), tj=120(degc max) 0 20 40 60 80 100 duty - turn on rate (%) 0 20 40 60 80 100 iout(ma) duty(%)-iout(ma) on pcb topr= 55 degree vdd=5.0v, vce=1.0(v), tj=120(degc max) 0 20 40 60 80 100 duty - turn on rate (%) 0 20 40 60 80 100 iout(ma) TB62726AFNA duty(%)-iout(ma) on pcb topr= 85 degree vdd=5.0v, vce=1.0(v), tj=120(degc max) 100 1000 10000 rext(ohms) 1 10 100 50 30 70 20 7 5 iout(ma) rext-iout (topr) vdd=3.3(v), vce=0.7(v) 0 10 20 30 40 50 60 70 80 90 ambient temperature ta (degree) 0 0.2 0.4 0.6 0.8 1 1.2 power dissipation pd (w/ic) afna (on pcb) ta(degree) - pd(w) TB62726AFNA
toshiba TB62726AFNA package dimmension p-ssop24-150-0.635 TB62726AFNA (ver.09) 2002, nov. 6 th page 10/11 1 12 24 13 0.0325 ref 0.025 0.008 ~ 0.012 0.229 ~ 0.244 0.150 ~ 0.157 0.337 ~0.344 0.004 ~ 0.010 0.053 ~ 0.068 0.016 ~ 0.034 0.007 ~ 0.009 unit : inch tentative
toshiba TB62726AFNA TB62726AFNA (ver.09) 2002, nov. 6 th page 11/11 the information contained herein is subject to change without notice. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patens or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others. toshiba is continually working to improve the quality and the reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a toshiba product could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within spacified operating ranges as set forth in the most recent products spacifications. also, please keep in mind the precautions and conditions set forth in the toshiba semiconductor reliability handbook. the products described in the document may include products subject to foreign exchange and foreign trade control laws. (c) 2000-2002 toshiba corporation all right reserved

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